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19-1900; Rev 0; 5/01
12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference
General Description
The MAX1421 is a +3.3V, 12-bit analog-to-digital converter (ADC), featuring a fully-differential input, pipelined, 12-stage ADC architecture with wideband track-and-hold (T/H) and digital error correction incorporating a fully-differential signal path. The MAX1421 is optimized for low-power, high-dynamic performance applications in imaging and digital communications. The converter operates from a single +3.3V supply, consuming only 188mW while delivering a typical signal-to-noise ratio (SNR) of 66dB at an input frequency of 15MHz and a sampling frequency of 40Msps. The fully-differential input stage has a small signal -3dB bandwidth of 400MHz and may be operated with single-ended inputs. An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure accommodates an internal or externally applied buffered or unbuffered reference for applications requiring increased accuracy or a different input voltage range. In addition to low operating power, the MAX1421 features two power-down modes, a reference power-down and a shutdown mode. In reference power-down, the internal bandgap reference is deactivated, resulting in a typical 2mA supply current reduction. For idle periods, a full shutdown mode is available to maximize power savings. The MAX1421 provides parallel, offset binary, CMOScompatible three-state outputs. The MAX1421 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified over the commercial (0C to +70C) and the extended industrial (-40C to +85C) temperature ranges. Pin-compatible higher- and lower-speed versions of the MAX1421 are also available. Please refer to the MAX1420 data sheet for a frequency of 60Msps and the MAX1422 data sheet for a frequency of 20Msps. o Single +3.3V Power Supply o 67dB SNR at fIN = 5MHz o 66dB SNR at fIN = 15MHz o Internal, +2.048V Precision Bandgap Reference o Differential, Wideband Input T/H Amplifier o Power-Down Modes 180mW (Reference Shutdown Mode) 10W (Shutdown Mode) o Space-Saving 48-Pin TQFP Package
Features
MAX1421
Ordering Information
PART MAX1421CCM MAX1421ECM TEMP. RANGE 0C to +70C -40C to +85C PIN-PACKAGE 48 TQFP 48 TQFP
Pin Configuration
AGND AVDD CML REFN REFP REFIN AVDD
48 47 46 45 44 43 42
41
40
39
38
AGND AVDD AVDD AGND AGND INP INN AGND AGND AVDD AVDD AGND
37
AGND PD OE D11 D10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
D9 D8 D7 D6 DVDD DVDD DGND DGND D5 D4 D3 D2
________________________Applications
Medical Ultrasound Imaging CCD Pixel Processing Data Acquisition Radar IF and Baseband Digitization
MAX1421
Functional Diagram appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
AGND AVDD AVDD AGND CLK CLK AGND AVDD DVDD DGND D0 D1
48-TQFP
1
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12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD to AGND..............................................-0.3V to +4V DVDD, AVDD to DGND..............................................-0.3V to +4V DGND to AGND.....................................................-0.3V to +0.3V INP, INN, REFP, REFN, REFIN, CML, CLK, CLK,....................(AGND - 0.3V) to (AVDD + 0.3V) D0-D11, OE, PD .......................(DGND - 0.3V) to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin TQFP (derate 12.5mW/C above +70C)........1000mW Maximum Junction Temperature .....................................+150C Operating Temperature Ranges MAX1421CCM ...................................................0C to +70C MAX1421ECM ................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V AVDD = V DVDD = +3.3V, AGND = DGND = 0, V IN = 1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity Mid-scale Offset Mid-scale Offset Temperature Coefficient RES DNL INL MSO MSOTC Internal reference (Note 1) Gain Error GE External reference applied to REFIN (Note 2) External reference applied to REFP, CML, and REFN (Note 3) Gain Error Temperature Coefficient GETC External reference applied to REFP, CML, and REFN, (Note 3) fIN = 5MHz fIN = 15MHz, TA = +25C fIN = 5MHz fIN = 15MHz, TA = +25C fIN = 5MHz fIN = 15MHz, TA = +25C fIN = 5MHz fIN = 15MHz, TA = +25C fIN = 5MHz fIN = 15MHz, TA = +25C fIN1 = 11.569MHz, fIN2 = 13.445MHz (Note 4) 60 60 64 62 -5 -5 -1.5 TA = +25C, no missing codes TA = TMIN to TMAX TA = TMIN to TMAX -3 -1 0.5 2 .75 3 10-4 0.1 3 0.5 15 10-6 5 5 1.5 %/C %FSR 3 12 1 Bits LSB LSB %FSR %/C SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (fCLK = 40MHz, 4096-point FFT) Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Signal-To-Noise Plus Distortion Effective Number of Bits Two-Tone Intermodulation Distortion SNR SFDR THD SINAD ENOB IMDTT 67 66 73 70 -74 -69 66 63.5 10.7 10.3 -80 -62 dB dBc dBc dB Bits dBc
2
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12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V AVDD = V DVDD = +3.3V, AGND = DGND = 0, V IN = 1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Differential Gain Differential Phase ANALOG INPUTS (INP, INN, CML) Input Resistance Input Capacitance Common-Mode Input Level, (Note 5) Common-Mode Input Voltage Range, (Note 5) Differential Input Range Small-Signal Bandwidth Large-Signal Bandwidth Over-Voltage Recovery RIN CIN VCML VCMVR VIN BW-3dB FPBW-3dB OVR VINP - VINN (Note 6) (Note 7) (Note 7) 1.5 FS input Either input to ground Either input to ground 32.5 4 VAVDD x 0.5 VCML 5% VDIFF 400 150 1 k pF V V V MHz MHz Clock Cycle SYMBOL DG DP CONDITIONS MIN TYP 1 0.25 MAX UNITS % degrees
MAX1421
INTERNAL REFERENCE (REFIN bypassed with 0.22F in parallel with 1nF) Common-Mode Reference Input Voltage Positive Reference Voltage Range Negative Reference Voltage Range Differential Reference Voltage Range Differential Reference Temperature Coefficient EXTERNAL REFERENCE REFIN Input Resistance REFIN Input Capacitance REFIN Reference Input Voltage Differential Reference Voltage RIN CIN VREFIN VDIFF VDIFF = (VREFP - VREFN) (Note 8) 5 10 2.048 10% 0.95 1.05 VREFIN/2 VREFIN/2 VREFIN/2 -200 15 200 k pF V V VCML VREFP VREFN VDIFF REFTC At CML At REFP At REFN VDIFF = VREFP - VREFN VAVDD 0.5 VCML + 0.512 VCML - 0.512 1.024 5% 100 V V V V ppm/C
EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN and CML) REFP, REFN, CML Input Current REFP, REFN, CML Input Capacitance IIN CIN A pF
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3
12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
ELECTRICAL CHARACTERISTICS (continued)
(V AVDD = V DVDD = +3.3V, AGND = DGND = 0, V IN = 1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Differential Reference Voltage Range CML Input Voltage Range REFP Input Voltage Range REFN Input Voltage Range SYMBOL VDIFF VCML VREFP VREFN CONDITIONS VDIFF = VREFP - VREFN MIN TYP 1.024 10% 1.65 10% VCML + VDIFF/2 VCML VDIFF/2 0.7 VDVDD 0.3 VDVDD CLK, CLK Input Current Input Capacitance DIGITAL OUTPUTS (D0-D11) Output Logic High Output Logic Low Three-State Leakage Three-State Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage Analog Supply Current Analog Supply Current with Internal Reference in Shutdown Analog Shutdown Current Digital Supply Current Digital Shutdown Current Power Dissipation Power-Supply Rejection Ratio TIMING CHARACTERISTICS Clock Frequency Clock High Clock Low fCLK tCH tCL Figure 5 Figure 5, clock period 25ns Figure 5, clock period 25ns 0.1 12.5 12.5 40 MHz ns ns PDISS PSRR IDVDD PD = DVDD Analog power (Note 9) 188 1 VAVDD VDVDD IAVDD REFIN = AGND PD = DVDD 5.5 20 214 3.135 2.7 3.3 3.3 52 50 3.465 3.6 65 63 20 V V mA mA A mA A mW mV/V VOH VOL IOH = 200A IOL = -200A VDVDD - 0.5 0 -10 2 VDVDD 0.5 10 V V A pF PD OE -20 -20 10 330 20 20 pF A MAX UNITS V V V V
DIGITAL INPUTS (CLK, CLK, OE, PD) Input Logic High Input Logic Low VIH VIL V V
4
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12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V AVDD = V DVDD = +3.3V, AGND = DGND = 0, V IN = 1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Pipeline Delay (Latency) Aperture Delay Aperture Jitter Data Output Delay Bus Enable Time Bus Disable Time tAD tAJ tOD tBE tBD SYMBOL Figure 5 Figure 9 Figure 9 Figure 5 Figure 4 Figure 4 5 CONDITIONS MIN TYP 7 2 2 10 5 5 14 MAX UNITS fCLK cycles ns ps ns ns ns
MAX1421
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Internal reference, REFIN bypassed to AGND with a combination of 0.22F in parallel with 1nF capacitor. External +2.048V reference applied to REFIN. Internal reference disabled. VREFIN = 0, VREFP = +2.162V, VCML = +1.65V, and VREFN = +1.138V. IMD is measured with respect to either of the fundamental tones. Specifies the common-mode range of the differential input signal supplied to the MAX1421. VDIFF = VREFP - VREFN Input bandwidth is measured at a 3dB level. VREFIN is internally biased to +2.048V through a 10k resistor. Measured as the ratio of the change in mid-scale offset voltage for a 5% change in VAVDD using the internal reference.
Typical Operating Characteristics
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
FFT PLOT, 4096-POINT RECORD, DIFFERENTIAL INPUT
MAX1421 toc01
FFT PLOT, 4096-POINT RECORD, DIFFERENTIAL INPUT
MAX1421 toc02
FFT PLOT, 4096-POINT RECORD, DIFFERENTIAL INPUT
fIN = 38.5440183MHz AIN = -0.49dB FS
MAX1421 toc03
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 0 5 10 15 fIN = 7.5439934MHz AIN = -0.45dB FS
0 -20 AMPLITUDE (dB) -40 HD2 -60 -80 -100 -120 HD3 fIN = 19.9047628MHz AIN = -0.50dB FS
0 -20 AMPLITUDE (dB) -40 HD2 -60 -80 -100 -120 HD3
HD2
HD3
20
0
5
10
15
20
0
5
10
15
20
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
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5
12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
TWO-TONE IMD, 8192-POINT RECORD, DIFFERENTIAL INPUT
MAX1421 toc04
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX1421 toc05
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX1421 toc06
0 -20 AMPLITUDE (dB) -40 -60
fIN1 = 11.5104229MHz fIN2 = 13.5126603MHz TWO-TONE ENVELOPE: -0.49dB FS AIN1 = AIN2 = -6.5dB FS fIN1 fIN2 IMD3
85
70
77 SFDR (dBc)
66
SNR (dB)
69
62
61
58
-80 -100 -120 0 2
IMD2 53 54
45 4 6 8 10 12 14 16 18 20 1 10 ANALOG INPUT FREQUENCY (MHz) 100 ANALOG INPUT FREQUENCY (MHz)
50 1 10 ANALOG INPUT FREQUENCY (MHz) 100
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1421 toc07
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1421 toc08
SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 15MHz)
MAX1421 toc09
-50
70
80 70 60
-56
66 SINAD (dB)
THD (dBc)
-62
62
SFDR (dBc)
50 40
-68
58
-74
54
30 20 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -60 -50 -40 -30 -20 -10 0 INPUT POWER (dB FS)
-80 1 10 ANALOG INPUT FREQUENCY (MHz) 100
50
SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 15MHZ)
70 60 THD (dBc) SNR (dB) -50
MAX1421 toc10
TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 15MHz)
MAX1421 toc11
SIGNAL-TO-NOISE PLUS DISTORTION vs. INPUT POWER (fIN = 15MHz)
MAX1421 toc12
80
-30
80
-40
60 SINAD (dB)
50 40 30 20 10 0 -60 -50 -40 -30 -20 -10 0 INPUT POWER (dB FS)
40
-60
20
-70
0
-80 -60 -50 -40 -30 -20 -10 0 INPUT POWER (dB FS)
-20 -60 -50 -40 -30 -20 -10 0 INPUT POWER (dB FS)
6
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12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE
MAX1421 toc13
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
MAX1421 toc14
TOTAL HARMONIC DISTORTION vs. TEMPERATURE
fIN = 5.51502MHz -72
MAX1421 toc15
84 fIN = 5.51502MHz 80 SFDR (dBc)
70 fIN = 5.51502MHz 68
-70
72
SNR (dB)
THD (dB)
76
66
-74
64
-76
68
62
-78
64 -40 -15 10 35 60 85 TEMPERATURE (C)
60 -40 -15 10 35 60 85 TEMPERATURE (C)
-80 -40 -15 10 35 60 85 TEMPERATURE (C)
MAX1421 toc17
fIN = 5.51502MHz 68 SINAD (dB)
MAX1421 toc16
1 INL (LSB) INL (LSB)
1 DNL (LSB)
0.25
66
0
0
0
64 -1 62 -2 -40 -15 10 35 60 85 -1
-0.25
60 TEMPERATURE (C)
-2 0
0
1024 2048 3072 1024 2048 3072 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE
4096 4096
-0.50 0 1024 2048 3072 4096 DIGITAL OUTPUT CODE
GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = +2.048V)
MAX1421 toc19
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX1421 toc20
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
CL 10pF 10 IAVDD (mA)
MAX1421 toc21
0.50
70
12
GAIN ERROR (%FSR)
0.25 IAVDD (mA)
60
0
50
8
-0.25
40
6
-0.50 -40 -15 10 35 60 85 TEMPERATURE (C)
30 -40 -15 10 35 60 85 TEMPERATURE (C)
4 -40 -15 10 35 60 85 TEMPERATURE (C)
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7
MAX1421 toc18
70
2
MAX1421 toc17
SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE
2
INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE vs. DIGITAL OUTPUT CODE
0.50
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
SFDR, SNR, THD, SINAD vs. CLOCK FREQUENCY
fIN = 5MHz SFDR, SNR, THD, SINAD (dB) 80 SFDR VREF (V)
MAX1421 toc22
INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX1421 toc23
90
2.0750
THD
2.0625
70
2.0500
60
SINAD
SNR
2.0375
50 10 18 26 34 CLOCK FREQUENCY (MHz)
2.0250 3.1 3.2 3.3 VDD (V) 3.4 3.5
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1421 toc24
OUTPUT NOISE HISTOGRAM (DC-INPUT)
45,000 40,000 35,000 43707
MAX1421 toc25
2.10
50,000
2.08
VREF (V)
2.06
COUNTS
30,000 25,000 20,000 15,000 10709 179 N-2 N-1 N N+1 10824
2.04
2.02
10,000 5000 1 N-3 116 N+2 0 N+3
2.00 -40 -15 10 35 60 85 TEMPERATURE (C)
0
DIGITAL OUTPUT NOISE
8
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12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference
Pin Description
PIN 1, 4, 5, 8, 9, 12, 13, 16, 19, 41, 48 2, 3, 10, 11, 14, 15, 20, 42, 47 6 7 17 18 NAME FUNCTION
MAX1421
AGND
Analog Ground. Connect all return paths for analog signals to AGND.
AVDD INP INN CLK CLK
Analog Supply Voltage. For optimum performance bypass to the closest AGND with a parallel combination of a 0.1F and a 1nF capacitor. Connect a single 10F and 1F capacitor combination between AVDD and AGND. Positive Analog Signal Input Negative Analog Signal Input Clock Frequency Input. Clock frequency input ranges from 100kHz to 40MHz. Complementary Clock Frequency Input. This input is used for differential clock inputs. If the ADC is driven with a single-ended clock, bypass CLK with a 0.1F capacitor to AGND. Digital Supply Voltage. For optimum performance bypass, to the closest DGND with a parallel combination of a 0.1F and a 1nF capacitor. Connect a single 10F and 1F capacitor combination between DVDD and DGND. Digital Ground Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB. Digital Data Outputs. D6 through D11, where D11 represents the MSB. Output Enable Input. A logic "1" on OE places the outputs D0-D11 into a high-impedance state. A logic "0" allows for the data bits to be read from the outputs. Shutdown Input. A logic "1" on PD places the ADC into shutdown mode. External Reference Input. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To disable the internal reference, connect REFIN to AGND. Positive Reference I/O. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. With the internal reference disabled (REFIN = AGND), REFP should be biased to VCML + VDIFF / 2. Negative Reference I/O. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. With the internal reference disabled (REFIN = AGND), REFN should be biased to VCML - VDIFF / 2. Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. With the internal reference disabled (REFIN = AGND).
21, 31, 32,
DVDD DGND D0-D5 D6-D11 OE PD REFIN
22, 29, 30 23-28 33-38 39 40 43
44 45 46
REFP REFN CML
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9
12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
Detailed Description
The MAX1421 uses a 12-stage, fully-differential, pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consumption. Each sample moves through a pipeline stage every halfclock-cycle. Including the delay through the output latch, the latency is seven clock cycles. A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code. The following digital-toanalog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held-input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage. This process is repeated until the signal has been processed by all 12 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. (OTA) input, and open simultaneously with S1, sampling the input waveform. The resulting differential voltage is held on capacitors C2a and C2b. Switches S4a and S4b are then opened before switches S3a and S3b, connecting capacitors C1a and C1b to the output of the amplifier, and switch S4c is closed. The OTA is used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first-stage quantizer and isolates the pipeline from the fast-changing input. The wide-input bandwidth, T/H amplifier allows the MAX1421 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs INP and INN can be driven either differentially or single-ended. Match the impedance of INP and INN and set the common-mode voltage to midsupply (AVDD / 2) for optimum performance.
Analog Input and Reference Configuration
The full-scale range of the MAX1421 is determined by the internally generated voltage difference between REFP (AVDD / 2 + VREFIN / 4) and REFN (AVDD / 2 V REFIN / 4). The MAX1421's full-scale range is adjustable through REFIN, which provides a high input impedance for this purpose. REFP, CML (AVDD / 2), and REFN are internally buffered low impedance outputs.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the input T/H circuit in both track-and-hold modes. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit passes the input signal to the two capacitors (C2a and C2b) throughswitches (S4a and S4b). Switches S2a and S2b set the common mode for the transconductance amplifier
MDAC VIN T/H x2 VOUT
INTERNAL BIAS S2a TO NEXT STAGE C1a
CML S5a S3a
FLASH ADC 2 BITS
DAC S4a OUT C2a S4c S1 OTA OUT S4b C2b C1b DIGITAL CORRECTION LOGIC 12 D11-D0 S2b INTERNAL BIAS S5b CML S3b
VIN
STAGE 1
STAGE 2
STAGE 12
Figure 1. Pipelined Architecture
Figure 2. Internal Track-and-Hold Circuit
10
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12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
AVDD 50 R 0.22F AVDD 2 R
MAX4284
CML 1nF
(AV2DD)
50 REFP R 0.22F 1nF
(AV2DD + 1V)
MAX1421
R AVDD 2 AVDD 4
MAX4284
R 50 REFN AVDD + 1V 2 0.22F AVDD 4 R REFIN R AGND 1nF
R
(
)
+1V
Figure 3. Unbuffered External Reference Drive--Internal Reference Disabled
The MAX1421 provides three modes of reference operation: * * * Internal reference mode Buffered external reference mode Unbuffered external reference mode
In internal reference mode, the on-chip +2.048V bandgap reference is active and REFIN, REFP, CML, and REFN are left floating. For stability purposes, bypass REFIN, REFP, REFN, and CML with a capacitor network of 0.22F, in parallel with a 1nF capacitor to AGND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In unbuffered external reference mode, REFIN is connected to AGND, which deactivates the on-chip buffers of REFP, CML, and REFN. With their buffers shut down, these nodes become high impedance and can be driven by external reference sources, as shown in Figure 3.
single-ended clock signal, bypass CLK with a 0.1F capacitor to AGND. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to have the lowest possible jitter. Any significant aperture jitter limits the SNR performance of the ADC according to the following relationship: 1 SNRdB = 20 x log10 2 x IN x t AJ where fIN represents the analog input frequency and tAJ is the aperture jitter. Clock jitter is especially critical for high input frequency applications. The clock input should always be considered as an analog input and routed away from any analog or digital signal lines. The MAX1421 clock input operates with a voltage threshold set to AVDD / 2. Clock inputs must meet the specifications for high and low periods, as stated in the Electrical Characteristics.
Clock Inputs (CLK, CLK)
The MAX1421's CLK and CLK inputs accept both single-ended and differential input operation, and accept CMOS-compatible clock signals. If CLK is driven with a
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11
12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
INP ADC INN AVDD
OUTPUT DATA D11-D0 HIGH-Z OE
D11-D0
tBE tBD HIGH-Z
VALID DATA
10k CLK 10k CLK AGND
10k
Figure 5. Output Enable Timing
10k
MAX1421
Figure 4. Simplified Clock Input Circuit
Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10k resistors to bias the common-mode level of each input. This circuit may be used to AC-couple the system clock signal to the MAX1421 clock input.
O Output Enable (OE), Power-Down (PD), and Output Data (D0-D11)
With OE high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power-down. All data outputs, D0 (LSB) through D11 (MSB), are TTL/CMOS-logic compatible. There is a seven clock-
cycle latency between any particular sample and its valid output data. The output coding is in offset binary format (Table 1). The capacitive load on the digital outputs D0 through D11 should be kept as low as possible (10pF), to avoid large digital currents that could feed back into the analog portion of the MAX1421, thereby degrading its dynamic performance. The use of digital buffers (e.g., 74LVCH16244) on the digital outputs of the ADC can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1421, add small-series resistors of 100 to the digital output paths, close to the ADC. Figure 5 displays the timing relationship between output enable and data output.
System Timing Requirements
Figure 6 depicts the relationship between the clock input, analog input, and data output. The MAX1421 samples at the rising edge of CLK (falling edge of CLK) and output data is valid seven clock cycles (latency) later. Figure 6 also displays the relationship between the input clock parameters and the valid output data.
Table 1. MAX1421 Output Code for Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF x 2047/2048 VREF x 2046/2048 VREF x 1/2048 0 -VREF x 1/2048 -VREF x 2046/2048 -VREF x 2047/2048 DIFFERENTIAL INPUT +FULL SCALE 1LSB +FULL SCALE 2LSB + 1 LSB Bipolar Zero - 1 LSB -FULL SCALE + 1 LSB -FULL SCALE OFFSET BINARY 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
Applications Information
Figure 7 depicts a typical application circuit containing a single-ended to differential converter. The internal reference provides an AVDD / 2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter at the input suppresses some of the wideband noise associated with high-speed op amps. Select the RISO and CIN values to optimize the filter performance and to suit a particular application. For the application in Figure 7, a RISO of 50 is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor. Connecting CIN from INN to INP may further improve dynamic performance.
* VREF = VREFP - VREFN
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12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
7 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6
ANALOG INPUT
CLK tDO CLK DATA OUTPUT N-7 N-6 N-5 N-4 N-3 N-2 N-1 N tCH tCL
Figure 6. System and Output Timing Diagram
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1421 for optimum performance. Connecting the center tap of the transformer to CML provides an AVDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a 1:2 or 1:4 step-up transformer may be selected to reduce the drive requirements. In general, the MAX1421 provides better SFDR and THD with fully differential input signals over singleended input signals, especially for very high input frequencies. In differential input mode, even-order harmonics are suppressed and each of the inputs requires only half the signal swing compared to singleended mode.
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application, using a MAX4108 op amp. This configuration provides high-speed, high-bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
network of a 10F bipolar capacitor in parallel with two ceramic capacitors of 1nF and 0.1F. Follow the same rules to bypass the digital supply DV DD to DGND. Multilayer boards with separate ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arrangement to match the physical location of the analog ground (AGND) and the digital output driver ground (DGND) on the ADCs package. The two ground planes should be joined at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer, DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces and remove digital ground and power planes from underneath digital outputs. Keep all signal lines short and free of 90 degree turns.
Static Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straightline can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1421 are measured using the best straight-line fit method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL
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Grounding, Bypassing, and Board Layout
The MAX1421 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass REFP, REFN, REFIN, and CML with a parallel network of 0.22F capacitors and 1nF to AGND. AVDD should be bypassed with a similar
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12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
+5V
0.1F LOWPASS FILTER MAX4108 300 0.1F RISO 50 0.1F CIN* 22pF INP
-5V
MAX1421
600 300 600 CML 0.1F +5V +5V 0.1F INPUT 0.1F MAX4108 300 0.1F MAX4108 INN RISO 50 0.1F CIN* 22pF LOWPASS FILTER 600 0.22F 1nF 0.1F 44pF*
-5V
300 -5V
300 300 300 *TWO CIN (22pF) CAPS MAY BE REPLACED BY ONE 44pF CAP, TO IMPROVE PERFORMANCE.
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
error specification of less than 1LSB guarantees no missing codes.
Dynamic Parameter Definitions
Aperture Jitter Figure 10 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 10). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of
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the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N-bits): SNR(MAX) = (6.02 N + 1.76)dB In reality, there are other noise sources besides quantization noise e.g., thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset.
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12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
25 22pF * 0.1F VIN N.C. 1 2 3 T1 6 5 4 0.22F 1nF 44pF * INP
MAX1421
CML
MINICIRCUITS T1-1T-KK81 25 22pF * INN
*REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN INP AND INN TO IMPROVE DYNAMIC PERFORMANCE.
Figure 8. Using a Transformer for AC-Coupling
VIN MAX4108 100
0.1F
RISO 50 CIN 22pF INP
1k
MAX1421
CML 1nF
0.22F
RISO 50 INN CIN 22pF
100
Figure 9. Single-Ended AC-Coupled Input Signal
CLK CLK
Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB is computed from: ENOB = SINADdB - 1.76dB 6.02dB
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
T/H
TRACK
HOLD
TRACK
Figure 10. Track-and-Hold Aperture Timing ______________________________________________________________________________________ 15
12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference MAX1421
Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as:
Functional Diagram
CLK CLK INTERFACE AVDD AGND
MAX1421
THD = 20 x log10
(V
2
2
+ V3 + V4 + V5 V1
2
2
2
)

INP T/H INN PIPELINE ADC
OUTPUT DRIVERS
D11-D0
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale and their envelope is at -0.5dB full scale.
PD
BANDGAP REFERENCE
REF SYSTEM + BIAS
DVDD DGND
REFIN REFP CML REFN
OE
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12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference
Package Information
32L/48L,TQFP.EPS
MAX1421
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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